An FPGA-BASED Digital Logic Core For ATE Support and Embbedded Test Applications

An FPGA-BASED Digital Logic Core For ATE Support and Embbedded Test Applications

From Summary:
        The Digital Logic Core is proposed in this thesis to address the technological
and economical challenges facing the IC test industry today. The DLC is a
customized circuit that is incorporated into the test environment to enhance the
testability of the DUT by supplementing automatic test equipment (ATE)
capabilities, providing a standalone test bed, or embedding test functionality into
larger systems.
        The enabling technology of the DLC is programmable logic, such as field-
programmable gate arrays (FPGAs), which off-loads the ATE test logic and
functions. Previous work used FPGAs for applications which required low speed,
but high test channel count. With the rapid advancement of FPGA technology, the
DLC can now perform most test functions of ATE while maintaining and exceeding
their performance. This level of complexity can be attained while drastically
reducing the cost of current test systems. Furthermore, the rapid development of
FPGA technology exceeds the rate of ATE improvement making this test strategy
more useful into the future.
        To demonstrate the feasibility of this concept, several applications are
developed and analyzed including an opto-electronic test bed for standalone
operation and a nano-scale wafer-level prober for embedded system operation.
These systems have been proven to operate at multi-gigahertz speeds which match
and exceed modern ATE specifications. More applications are planned for the near
future which far exceed these rates.

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